Term
The decimal number 13 can be represented as the binary string
a. 101101
b. 001011
c. 001101
d. None of the above |
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The decimal number -13 can be represented using 2’complement representation as:
a. 101101
b. 110011
c. 111010 |
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Consider two integers A and B represented as 2’s complement numbers A = 11110101 and B = 01010101
a. A is larger than B
b. B is larger than A
c. A and B are equal |
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In 2's complement arithmetic, an overflow during addition occurs if:
a. two positive numbers produce a negative result
b. two negative numbers produce a positive result
c. both a and b
d. neither a nor b |
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Term
Let A=100101 and B = 010111 (using 2’s complement representation). What is A+B
represented in 2’s complement? |
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Definition
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Term
The decimal digit 11 can be represented as the bit string:
a. 101101
b. 001011
c. 001101
d. None of the above |
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Definition
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Term
The decimal digit -11 can be represented using 2’complement representation as the bit string:
a. 101101
b. 101011
c. 110101 |
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Definition
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Term
Two values A = 00000110 and B = 11111101 are two integers represented using 2’s complement notation.
a. A is larger
b. B is larger
c. A and B are equal |
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Definition
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Term
In 2's complement arithmetic, an overflow during addition occurs if:
a. a positive number and a negative number produce a negative result
b. a positive number and a negative number produce a positive result
c. both a and b
d. neither a nor b addition of negative and positive can never lead to an overflow |
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Definition
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Term
Let A=110101 and B = 010010 (using 2’s complement representation). What is A+B
represented in 2’s complement? |
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Definition
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Term
Provide the truth table for the Boolean function – you can just provide the values for F (i.e., you do not have to fill out all the columns in the table).
F= ((A AND B) OR (C AND (NOT C)) |
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Definition
Either work through a truth table, or apply Boolean algebra laws to simplify:
(C AND NOT C) = 0 , therefore F= (A OR B) OR 0 = (A AND B) – C does not play a role.
Truth table is simply the truth table for A AND B, F=1 when A=1 and B=1 and 0 otherwise. |
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What does the function WhoamI(x,n) do? Give your answer in terms of the inputs x and n. Assume 32 bit integers and assume n is between 0 and 3 (i.e., it is not less than 0 and not greater than 3). Note that 0xFF is hex notation for decimal number 255 as a 32 bit integer. Briefly justify your answer.
int WhoamI(int x, int n) {
int y = n << 3;
int xs = 0xFF << y;
return xs & x;
} |
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Definition
int WhoamI(int x, int n) {
int y = n << 3; /* shift n 3 places to left, therefore y = n*8 */
int xs = 0xFF << y; /* shift xFF (8n) places to left */
/* this gives us a mask where we have 8 1’s – or FF – in the n-th byte of the 32 bit word */
return xs & x;/* mask out everything except the n-th bytet */
/* function extracts and returns the n-th byte in the input x */
} |
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Determine if the two statements below are True or False
All LC-3 instructions require the FETCH and DECODE phases of the instruction cycle for correct processing.
The LC-3 ISA specifies an instruction which accesses two memory locations, adds their contents, and stores the sum in another memory location. |
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The Fetch phase of the Instruction execution process requires the ______.
a. Program Counter
b. Offset
c. Opcode
d. Register R1 |
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Definition
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Term
Reading and writing to the memory unit (RAM, or off-processor memory) in the von Neumann model takes place via:
a. the ALU and the register unit
b. the memory address register and memory data register
c. the program counter and the memory data register
d. the Program Counter and the Instruction Register |
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Term
The LC3 JMP instruction is an example of a
a. operate instruction
b. control instruction
c. data movement instruction
d. none of the above |
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Definition
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| If the 16-bit LC-3 ISA was modified to specify 32 general purpose registers and every other specification remained unchanged (i.e., 15 opcodes and same instruction set as original case), would it be possible to encode an ADD instruction that uses 2 source registers and one destination register? The instruction needs to specify opcode, source and destination registers, and 1 bit for addressing mode (register or immediate). |
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Definition
| If we have 32 registers, we need 5 bits to encode the registers. The ADD instruction requires 4 bits for opcode, 5 bits for destination, and 5 bits each for the two source registers, and 1 bit for addressing mode (immediate or register). This totals to (4+5+5+5+1)=20 bits. Therefore it is not possible to encode the ADD instruction using 16 bit instructions. |
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Determine if the two statements below are True or False
There is a single LC3 instruction that copies data from one memory location to another memory location.
The execute phase is not required for some instructions |
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Definition
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| If the 16-bit LC-3 ISA was modified to specify 64 general purpose registers and every other specification remained unchanged (i.e., 15 opcodes and same instructions as original case), would it be possible to encode an AND instruction that uses 2 source registers and one destination register? The instruction needs to specify opcode, source and destination registers, and 1 bit for addressing mode (register or immediate). |
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Definition
| If we have 64 registers, we need 6 bits to encode the registers. The AND instruction requires 4 bits for opcode, 6 bits for destination, and 6 bits each for the two source registers, and 1 bit for addressing mode (immediate or register). This totals to (4+6+6+6+1)=23 bits. Therefore it is not possible to encode the ADD instruction using 16 bit instructions. |
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Term
The LC3 LDR instruction is an example of a
a. operate instruction
b. control instruction
c. data movement instruction
d. none of the above |
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Definition
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Term
The Decode phase of the Instruction execution process requires the ______.
a. Program Counter
b. Offset
c. Opcode
d. Register R1 |
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Definition
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Term
The memory, in a von Neuman computer (such as LC3) contains:
a. Instructions only
b. data only
c. both instructions and data.
d. Neither instructions nor data. |
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