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| The brain of the computer; alternatively known as CPU |
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| What is the grand-daddy of all CPUs? |
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| External Data Bus; enables communication with the CPU; "lightbulb" system |
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| General-Purpose Registers |
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| Where the CPU places code before exporting it to the EDB |
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| Clock wire; wire that activates the CPU |
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| A single charge to the clock wire; millions of time a second |
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| Max number of clock cycles a CPU can handle; ranges from 4.77 MHz (4.7 million/sec) to 4 GHz (4 billions/sec) |
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| Quartz oscillator that determines the speed at which the CPU and the rest of the PC operate |
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| Intentionally running a CPU at a higher clock speed than it is built for |
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| Series of commands sent to a CPU in a specific order in order to perform work |
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| Devices that hold ones and zeros |
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| An if-statement; when combined with memory, allows CPUs to store not only programs but also the results of programs |
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| Dynamic RAM; RAM that requires power and occasional refresh of circuits |
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| Memory Controller Chip; controls what code moves from the RAM to the EDB |
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| Allows the CPU to communicate to the MCC what code it needs from the RAM; 2^[#of address bus wires] = bytes of RAM CPU can handle |
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| # of bytes of RAM a CPU can handle; 2^[#of address bus wires] |
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| Who are the main manufacturers of CPUs? |
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| Pin-Grid Array; CPU packaging in a square with hundreds of pins |
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| Zero Insertion Force Sockets; sockets that use an arm to hold the CPU in, so it doesn't snap in |
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| CPUs that have a 32 wire address bus and 32 bit registers |
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| What are the four processes of a CPU? |
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| Fetch, Decode, Execute, and Write |
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| Conveyer-belt style processing where all four circuits are Fetching, Decoding, Executing, or Writing every clock cycle |
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| When a single stage of processing requires more than one clock cycle |
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| Circuit that handles basic math with no decimal points; 90% of processing is here; very fast |
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| Floating Point Unit; does complex mathematics, takes many clock-cycles to function |
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| Intel gave the Pentium one main, do-everything pipeline, and one for only integer mathematics |
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| A series of instructions sent from a program to the CPU |
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| Stalls when the RAM cannot supply code fast enough to the CPU |
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| Static RAM; preloads as many instructions and data as possible in hopes that the CPU would need them again |
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| First cache the CPU tries to use |
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| Second cache the CPU checks |
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| CPU uses a counter to predict whether the information in the cache would be useful or not at if-statements |
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| Multiplies the incoming clock signal to make the circuitry move faster by sending code from cache to cache rather than to the EDB |
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| Electrical switches that allow the APU to handle code |
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| Voltage Regulator Module; Dampens down voltages for the CPU; now are obsolete |
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| The ability to execute more than one instruction in any one clock cycle |
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| Ability for a CPU to process data out of order during a wait state |
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| Predicting the result of an if-statement and running the result before running the branch itself as part of out-of-order processing |
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| The address bus and the external data bus (connecting the CPU, MCC, and RAM) |
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| Connects the CPU and the L2 cache (on-chip) |
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| Multi-Media Extensions; increases multipliers/clocks and improves processing for graphics |
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| Single Edge Cartridge; physical change in the packaging to allow for better cooling and more room for the L2 cache |
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| Quad-Pumped Frontside Bus |
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| EDB is sampled for instruction four times per clock cycle |
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| Each pipeline can run more than one thread; appears to the computer as multiple CPUs |
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| System Management Mode; provides the CPU with the capability to turn off devices that use a lot of power |
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| Allows CPUs to slow themselves down during low-demand times; Intel's "SpeedStep" and AMD's "PowerNow!" |
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| Do 64-bit CPUs use a 64-bit Address Bus? |
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| No; there's no need. 64-bit address busses allow for 16 Exabytes of RAM |
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| What was unique about Intel's first 64-bit processors? |
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| They weren't backwards-compatible with 32-bit operating systems |
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| What did integration of the memory controller into the CPU result in? |
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| Elimination of the external MMC and eliminating of the idea of the frontside bus |
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| Two CPUs in a single chip; two sets of pipelines, but shared caches and RAM |
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| Processing multiple threads in separate cores at a single time |
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| Four cores that have individual L1 &2 cores, but share an L3 core |
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| QuickPath Interconnect; alternative to the frontside bus |
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| Single Edge Processor; identical to the SEC, but without the protective casing |
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| What is the single most important piece of documentation for replacing your CPU? |
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| What two items are necessary when replacing a CPU? |
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| A proper heat-sink and cooling system (fan or liquid) |
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| Also Head-Dope; a compound spread on the CPU to prevent overheating |
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| How long (max) should the CPU run without the fan after replacing the CPU? |
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