Term
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Definition
| The Program Counter, PC. It always points to the next instruction to be fetched. |
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Term
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Definition
| Stack Pointer, SP. where the CPU stores the address's for the stack or interrupts. |
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Term
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Definition
| The Status Register, or constant generator 1. Defines the current status of the register in several bits. It also serves to generate constants 4 and 8. Defines Register mode or absolute mode. |
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Term
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Definition
| Constant generator. Generates constants 0, 1, 2, -1 |
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Term
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Definition
| General Purpose registers |
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Term
| Double Operand instructions |
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Definition
There are 12. Include; ADD, XOR, CMP
refer to Ch. 3, slide 10 |
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Term
| Single Operand Instructions |
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Definition
There are 7. Including RRA, PUSH, CALL, RETI
ref Ch. 3, slide 12 |
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Term
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Definition
| Conditions consisting of three bits |
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Term
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Definition
| 24 emulated instructions.Do not have specific Op-Codes. |
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Term
| Source/Destination: Register Mode |
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Definition
Rn
example: mov.w r5, r6 move word from r5 to r6
It is the fastest mode because it does not require an additional clock cycle.
0101 - 0001 - 1 - 0 - 01 - 0101
opcod src ad B/W As dst |
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Term
| Source/Destination: Indexed Mode |
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Definition
x(Rn)
Adds constant x to the contents stored in a register and uses the new number as the address for the source
Example: mov.b 3(r5), 56 move byte M(310+r5) to r6
The index is located in the memory word following the instruction and requires an additional memory cycle
There is no restriction on the address for a byte, but words must lie on even addresses
0101 - 1010 - 1 - 0 - 01 - 1011
opcod s-reg ad b/w As dest |
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Term
| Source/Destination: Symbolic Mode |
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Definition
The address if formed by adding a constant (index) to the program counter (PC)
Example: (mov.w x(PC), r6 where x=Cnt-PC)
mov.w Cnt,r6 ; move word
; M(Cnt) or M(x+PC) to r6
The PC relative index is calculated by the assembler
Produces position-independent code, but rarely used in the MSP430 because absolute addressing can reach all memory addresses
Note: this is NOT an appropriate mode of addressing when referencing fixed locations in memory such as the special function registers (SFR’s) |
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Term
| Source/Destination: Absolute Mode |
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Definition
The address is formed directly from a constant (index) and specified by preceding a label with an ampersand (&)
Example: (mov.w x(SR), r6 where 0 is used for SR)
mov.w &Cnt,r6 ; move word
; M(Cnt) to r6
Same as indexed mode with the base register value of 0 (by using the status register SR as the base register)
The absolute address is stored in the memory word following the instruction and requires an additional cycle
Note: this is the preferred mode of addressing when referencing fixed locations in memory such as the special function registers (SFR’s) |
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Term
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Definition
The address of the operand is formed from the contents of the specified register
Example:
mov.w @r5,r6 ; move word
; M(r5) to r6
Only available for source operands
Same as indexed mode with index equal to 0, but does not require an additional instruction word
The value of the indirect register is unchanged |
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Term
| Source: Indirect Auto Increment |
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Definition
The address of the operand is formed from the contents of the specified register and afterwards, the register is automatically increment by 1 if a byte is fetched or by 2 if a word is fetched
Example:
mov.w @r5+,r6 ; move word
; M(r5) to r6
; increment r5 by 2
Only available for source operands.
Usually called post-increment addressing.
Note: All operations on the first address are fully completed before the second address is evaluated |
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Term
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Definition
The operand is an immediate value
Example (mov.w @PC+, r6)
mov.w #100,r6 ; 100 -> r6
The immediate value is located in the memory word following the instruction
Only available for source operands
The immediate mode of addressing is a special case of auto-increment addressing that uses the program counter (PC) as the source register.
The PC is automatically incremented after the instruction is fetched; hence points to the following word |
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Term
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Definition
mov.w R5, R6 ; move the content of R5 (0010) to R6
mov.w @R7, R8 ; use the content of R7 (9000) as the address to move data (000F) to R8
mov.w &0x9004, R6 ; go to the absolute address (9004) to move data (0011) to R6
mov.w 2(R7), R9 ; use the content of R7 (9000) as the base address and offset it by 2 (9002) to move data (0010) to R9
mov.w &0x9006, R5 ; go to the absolute address (9006) to move data (0012) to R5
mov.w @R7+, R6 ; use the content of R7 (9000) as the address to move data (000F) to R6 and then increment R7 by 2 (one word is 2 bytes)
mov.w #0x9000, R7 ; move the immediate value (9000) to R7
mov.w label, R7 ; move the data (0012) in the memory space represented by “label” to R7 |
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Term
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Definition
mov.w R5, R6 ; move the content of R5 (0010) to R6
mov.w R5, 4(R7) ; use the content of R7 (9000) as the base address and offset it by 4 (9004) and move the content of R5 (0010) to the effective address (9004)
mov.w R6, label ; move the content of R6 (0012 moved from R5) to the memory space represented by “label”
mov.w &0x9004, &0x9008 ; go to the absolute address (9004) to move data (0011) to the memory location of the absolute address (9008)
mov.w R6, &label ; move the content of R6 (0012 moved from R5) to the memory space represented by the absolute address “label” |
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Term
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Definition
Finiteness
Must terminate.
Definiteness
Each step is precisely stated.
Effective Computability
Each step can be carried out. |
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Term
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Definition
Construct Symbol Table
Find the .text statement and zero the Location Counter (LC)
For each non-empty line in the program:
If line contains a label, add label and current LC to the symbol table
If line contains an instruction, increment the LC accordingly
1. All instructions are 2, 4, or 6 bytes in length
2. Some directives like .bss or .string increment LC by the size of the operand.
Stop when .end statement is reached. |
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Term
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Definition
Generate Machine Code
Reset location counter (LC)
For each executable assembly language statement, generate the corresponding machine language instruction.
resolve labels referenced in instructions using the symbol table
increment LC for each instruction as in pass 1
output resulting machine code and program listing to output files
Stop when .end statement is reached. |
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Term
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Definition
Stacks are the fundamental data structure of computers today
A stack is a last in, first out (LIFO) abstract data type
A stack is a restricted data structure with two fundamental operations, namely push and pop
Elements are removed from a stack in the reverse order of their addition |
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Term
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Definition
| In a stack, the data does not move in memory, just the pointer to the top of stack. |
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Term
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Definition
A subroutine is “called” in assembly with a CALL instruction.
The address of the next instruction after the subroutine call is saved by the processor onto the stack.
Local variables are pushed/popped from the stack.
At the end of a subroutine, a RET instruction “pops” the top value from the stack into the program counter. |
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Term
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Definition
At beginning of routine, save all registers that will be altered (unless altered value is desired by calling program!)
Before returning, restore those same registers in reverse order |
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Term
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Definition
Should be short and fast
Should affect the rest of the system as little as possible
Require a balance between doing very little – thereby leaving the background code with lots of processing – and doing a lot and leaving the background code with nothing to do |
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Term
| Applications that use interrupts should: |
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Definition
Disable interrupts as little as possible
Respond to interrupts as quickly as possible
Communicate w/ISR only through global variables (never through registers!!!) |
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Term
| Common interrupt-related errors include: |
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Definition
Failing to protect global variables
Forgetting to actually include the ISR - no linker error!
Not testing or validating thoroughly
Stack overflow
Running out of CPU horsepower
Interrupting critical code
Trying to outsmart the compiler |
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Term
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Definition
| the 6 cycle delay before an isr begins executing |
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Term
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Definition
| the end of a isr, it takes 5 cycles to execute |
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Term
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Definition
Active Mode (AM): CPU, all clocks, and enabled modules are active (300 A)
LPM0: CPU and MCLK are disabled, SMCLK and ACLK remain active (85 A)
LPM3: CPU, MCLK, SMCLK, and DCO are disabled; only ACLK remains active (1 A)
LPM4: CPU and all clocks disabled, RAM is retained (0.1 A) |
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Term
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Definition
Active 0 0 0 0
LPMO 0 0 0 1
LPM3 1 1 0 1
LPM4 1 1 1 1
SCG1 SCG0 OSC CPU 0 = on |
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Term
| Principles of Low-Power Apps |
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Definition
Maximize the time in LPM3 mode
Use interrupts to wake the processor
Switch on peripherals only when needed
Use low-power integrated peripherals
Timer_A and Timer_B for PWM
Calculated branches instead of flag polling
Fast table look-ups instead of calculations
Avoid frequent subroutine and function calls
Longer software routines should use single-cycle CPU registers |
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Term
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Definition
Constants
The assembler maintains constants internally as a 32-bit, signed (2’s complement) or unsigned numbers
Constants are not sign extended
The pound sign precedes a constant in an instruction
mov #123,r15
Types of constants:
Decimal: string of decimal digits ranging from -2147483648 to 4294967295 (ie, 1000, -32768)
Hexadecimal: string of up to 8 hexadecimal digits followed by suffix ‘H’ (or ‘h’) or preceded by ‘0x’ (ie, 78h, 0x78)
Binary: string of up to 32 binary digits followed by suffix B (or b) (ie. 0000b, 11110000B) |
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Term
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Definition
Expressions
An expression is a constant, a symbol, or a series of constants and symbols separated by arithmetic operators
An expression evaluates to a 32-bit number
-2147483648 to 2147483647 for signed values
0 to 4294967295 for unsigned values
The precedence order of expression evaluation is
First, evaluate parenthesized expressions
Second, evaluate operators according to precedence groups
Third, when parentheses and precedence groups do not determine the order of expression evaluation, the expressions are evaluated from left to right |
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Term
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Definition
The assembler translates assembly language programs (.asm) into the machine language of the ISA (.obj)
There is a 1-to-1 correspondence between assembly language instructions and instructions in the final machine language
First Pass:
find all labels and their corresponding addresses - this information is stored in the symbol table
Second Pass:
convert instructions to machine language, using information from symbol table, report undefined symbols |
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Term
| 1st Pass: Construct Symbol Table |
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Definition
Find the .text assembly directive and zero the Location Counter ($)
For each non-empty line in the program:
If line contains a label, add label and current LC to the symbol table
If line contains an instruction, increment the LC accordingly
1. All instructions are 2, 4, or 6 bytes in length
2. Some directives like .bss or .string increment LC by the size of the operand.
Stop when .end directive is found. |
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Term
| 2nd Pass: Generate Machine Language |
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Definition
Reset location counter (LC)
For each executable assembly language statement, generate the corresponding machine language instruction
resolve labels referenced in instructions using the symbol table
increment LC for each instruction as in pass 1
output resulting machine code and program listing to output files
Stop when .end directive is found. |
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Term
| Assembly Style Guidelines |
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Definition
Provide a program header, with author’s name, date, etc., and purpose of program.
Start labels, opcode, operands, and comments in same column for each line. (Unless entire line is a comment.)
Use comments to explain what each register does.
Remember, the assembler is case sensitive.
Use meaningful symbolic names.
Mixed upper and lower case for readability.
ASCIItoBinary, InputRoutine, SaveR1
Provide comments between program sections.
Each line must fit on the page -- no wraparound or truncations.
Long statements split in aesthetically pleasing manner. |
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Term
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Definition
eZ430-F2013 Development Tool
P1.0 Green LED
Enable port bit for output by writing a 1 to the port direction register
bis.b #0x01,&P1DIR ; P1.0 output
Turn LED off by writing a 0 to the port pin
bic.b #0x01,&P1OUT ; turn off LED
Turn LED on by writing a 1 to the port pin
bis.b #0x01,&P1OUT ; turn on LED
Toggle LED by XOR’ing a 1 to the port pin
xor.b #0x01,&P1OUT ; toggle LED |
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Term
| Add Source to Destination |
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Definition
ADD Add source word or byte to destination
Syntax ADD{.W or .B} src,dst
Operation src + dst −> dst
Description The source operand is added to the destination operand. The source operand is not affected. The previous contents of the destination are lost.
Status Bits N: Set if result is negative, else reset
Z: Set if result is zero, else reset
C: Set if there is a carry, else reset V: Set if an arithmetic overflow, else reset
Example ADD #10,R5
JC TONI ; Carry occurred
...... ; No carry |
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Term
| Add Source/Carry to Destination |
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Definition
ADDC Add source word or byte and carry to destination
Syntax ADDC{.W or .B} src,dst
Operation src + dst + C −> dst
Description The source operand and the carry bit (C) is added to the destination operand. The source operand is not affected. The previous contents of the destination are lost.
Status Bits N: Set if result is negative, else reset
Z: Set if result is zero, else reset
C: Set if there is a carry, else reset
V: Set if an arithmetic overflow, else reset
Example ADD.W @R13+,10(R13) ; ADD LSDs
ADDC.W @R13+,10(R13) ; ADD 2/carry |
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Term
| AND Source to Destination |
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Definition
AND Source AND destination
Syntax AND{.W or .B} src,dst
Operation src .AND. dst −> dst
Description The source operand and the destination operand are logically ANDed. The result is placed into the destination.
Status Bits N: Set if result MSB is set, else reset
Z: Set if result is zero, else reset
C: Set if result is not zero, else reset
V: Reset
Example MOV #0AA55h,R5 ; Load mask
AND R5,TOM ; mask M(TOM)
JZ TONI |
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Term
| Clear Bits in Destination |
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Definition
BIC Clear bits in destination
Syntax BIC{.W or .B} src,dst
Operation .NOT.src .AND. dst −> dst
Description The inverted source operand and the destination operand are logically ANDed. The result is placed into the destination. The source operand is not affected.
Status Bits Status bits are not affected.
Example
BIC.W #0FC00h,LEO ; Clear 6 MSBs
BIC.B #0F8h,LEO ; Clear 5 MSBs |
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Term
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Definition
BIS Set bits in destination
Syntax BIS{.W or .B} src,dst
Operation src .OR. dst −> dst
Description The source operand and the destination operand are logically ORed. The result is placed into the destination. The source operand is not affected.
Status Bits Status bits are not affected.
Example
BIS.W #003Fh,TOM ; set the 6 LSBs
BIS.B #0E0h,TOM ; set the 3 MSBs |
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Term
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Definition
BIT Test bits in destination
Syntax BIT{.W or .B} src,dst
Operation src .AND. dst
Description The source and destination operands are logically ANDed. The result affects only the status bits. The source and destination operands are not affected.
Status Bits N: Set if MSB of result is set, else reset
Z: Set if result is zero, else reset
C: Set if result is not zero, else reset
V: Reset
Example BIT #0200h,R8 ; bit 9 of R8 set?
JNZ TOM ; Y |
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Term
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Definition
CALL Subroutine
Syntax CALL dst
Operation dst −> tmp dst is evaluated and stored
SP − 2 −> SP
PC −> @SP PC updated to TOS
tmp −> PC dst saved to PC
Description A subroutine call is made to an address anywhere in the 64K address space.
All addressing modes can be used. The return address (the address of the following instruction) is stored on the stack. The call instruction is a word instruction.
Status Bits Status bits are not affected. |
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Term
| Compare Source and Destination |
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Definition
CMP Compare source and destination
Syntax CMP{.W or .B} src,dst
Operation dst + .NOT.src + 1 or (dst − src)
Description The source operand is subtracted from the destination operand. The two operands are not affected and the result is not stored; only the status bits are affected.
Status Bits N: Set if result is negative, else reset
Z: Set if result is zero, else reset
C: Set if carry from the MSB, else reset
V: Set if an arithmetic overflow, else reset
Example CMP R5,R6 ; R5 = R6?
JEQ EQUAL ; YES, JUMP |
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Term
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Definition
Jxx Jump if carry set
Syntax Jx label
Operation If condition true: PC + 2 × offset −> PC
Description If condition is true, the LSB 10-bit signed offset contained in the instruction is added to the program counter. Else the next instruction following the jump is executed.
Status Bits Status bits are not affected.
Examples JC, JHS Jump if carry (C) = 1
JEQ, JZ Jump if zero (Z) = 1
JGE Jump if (N .xor. V) = 0
JL Jump if (N .xor. V) = 1
JMP Jump unconditionally
JN Jump if negative (N) = 1
JNC, JLO Jump if carry (C) = 0
JNE, JNZ Jump if zero (Z) = 0 |
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Term
| Move Source to Destination |
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Definition
MOV Move word or byte source to destination
Syntax MOV{.W or .B} src,dst
Operation src −> dst
Description The source operand is moved to the destination. The source operand is not affected. The previous contents of the destination are lost.
Status Bits Status bits are not affected.
Example MOV #EDE,R10 ; Prepare pointer
MOV #020h,R9 ; Prepare counter |
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Term
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Definition
PUSH Push word or byte onto stack
Syntax PUSH{.W or .B} src
Operation SP − 2 → SP
src → @SP
Description The stack pointer is decremented by two, then the source operand is moved to the RAM word addressed by the stack pointer (TOS).
Status Bits Status bits are not affected.
Example PUSH R8 ; save R8
Note The system stack pointer (SP) is always decremented by two, independent of the byte suffix. |
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Term
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Definition
RETI Return from interrupt
Syntax RETI
Operation TOS → SR; SP + 2 → SP
TOS → PC; SP + 2 → SP
Description The status register is restored to the value at the beginning of the interrupt service routine by replacing the present SR contents with the TOS contents. The stack pointer (SP) is incremented by two. The program counter is restored to the value at the beginning of interrupt service. The stack pointer (SP) is again incremented by 2.
Status Bits N, Z, C, V: restored from system stack
Mode Bits OSCOFF, CPUOFF, and GIE are restored from system stack. |
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Term
| Rotate Right Arithmetically |
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Definition
RRA Rotate word or byte right arithmetically
Syntax RRA{.W or .B} dst
Operation MSB MSB, MSB MSB−1, ... LSB+1 LSB, LSB C
Description The destination operand is shifted right one position. The MSB is shifted into the MSB, the MSB is shifted into the MSB−1, and the LSB+1 is shifted into the LSB.
Status Bits N: Set if result is negative, else reset
Z: Set if result is zero, else reset
C: Loaded from the LSB
V: Reset
Example RRA R5 ; R5/2 −> R5 |
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Term
| Rotate Right Through Carry |
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Definition
RRC Rotate word or byte right through carry
Syntax RRC{.W or .B} dst
Operation C MSB MSB−1 .... LSB+1 LSB C
Description The destination operand is shifted right one position. The carry bit (C) is shifted into the MSB, the LSB is shifted into the carry bit (C).
Status Bits N: Set if result is negative, else reset
Z: Set if result is zero, else reset
C: Loaded from the LSB
V: Reset
Example SETC ; Prepare carry for MSB
RRC R5 ; R5/2 + 8000h −> R5 |
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Term
| Subtract Source from Destination |
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Definition
SUB Subtract word or byte source from destination
Syntax SUB{.W or .B} src,dst
Operation dst + .NOT.src + 1 −> dst
Description The source operand is subtracted from the destination operand by adding the source operand’s 1s complement and the constant 1. The source operand is not affected. The previous contents of the destination are lost.
Status Bits N: Set if result is negative, else reset
Z: Set if result is zero, else reset
C: Set if there is a carry, else reset
Set to 1 if no borrow, reset if borrow.
V: Set if an arithmetic overflow, else reset
Note: The borrow is treated as a .NOT. Carry |
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Term
| Subtract Source and Borrow from Destination |
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Definition
SUBC Subtract source and borrow from destination
Syntax SUBC{.W or .B} src,dst
Operation dst + .NOT.src + C −> dst
Description The source operand is subtracted from the destination operand by adding the source operand’s 1s complement and the carry bit (C). The source operand is not affected. The previous contents of the destination are lost.
Status Bits N: Set if result is negative, else reset
Z: Set if result is zero, else reset
C: Set if there is a carry, else reset
Set to 1 if no borrow, reset if borrow.
V: Set if an arithmetic overflow, else reset |
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Term
| Subtract Source and Borrow from Destination |
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Definition
SUBC Subtract source and borrow from destination
Syntax SUBC{.W or .B} src,dst
Operation dst + .NOT.src + C −> dst
Description The source operand is subtracted from the destination operand by adding the source operand’s 1s complement and the carry bit (C). The source operand is not affected. The previous contents of the destination are lost.
Status Bits N: Set if result is negative, else reset
Z: Set if result is zero, else reset
C: Set if there is a carry, else reset
Set to 1 if no borrow, reset if borrow.
V: Set if an arithmetic overflow, else reset |
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Term
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Definition
SWPB Swap bytes
Syntax SWPB dst
Operation Bits 15 to 8 <−> bits 7 to 0
Description The destination operand high and low bytes are exchanged.
Status Bits Status bits are not affected.
Example The value in R5 is multiplied by 256. The result is stored in R5,R4.
SWPB R5 ; swap bytes in r5
MOV R5,R4 ; save in r4
BIC #0FF00h,R5 ;Correct the result
BIC #00FFh,R4 ;Correct the result |
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Term
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Definition
SXT Extend Sign
Syntax SXT dst
Operation Bit 7 −> Bit 8 ......... Bit 15
Description The sign of the low byte is extended into the high byte.
Status Bits N: Set if result is negative, else reset
Z: Set if result is zero, else reset
C: Set if result is not zero, else reset
V: Reset
Example MOV.B &P1IN,R7 ; read port 1
SXT R7 ; sign extend to 16 |
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Term
| Exclusive OR Source w/Destination |
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Definition
XOR Exclusive OR word or byte source with destination
Syntax XOR{.W or .B} src,dst
Operation src .XOR. dst −> dst
Description The source and destination operands are exclusive ORed. The result is placed into the destination. The source operand is not affected.
Status Bits N: Set if result MSB is set, else reset
Z: Set if result is zero, else reset
C: Set if result is not zero, else reset
V: Set if both operands are negative, else reset
Example XOR R6,TONI ; Toggle bits |
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Term
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Definition
ADC Add word or byte carry to destination
Syntax ADC{.W or .B} dst
Operation dst + C −> dst
Emulation ADDC{.W or .B} #0,dst
Description The carry bit (C) is added to the destination operand. The previous contents of the destination are lost.
Status Bits N: Set if result is negative, else reset
Z: Set if result is zero, else reset
C: Set if dst was incremented from 0xFFFF to 0x0000, else reset
V: Set if an arithmetic overflow, else reset
Example ADD @R13,0(R12) ; Add LSDs
ADC 2(R12) ; Add carry to MSD |
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Term
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Definition
CLR Clear word or byte destination
Syntax CLR{.W or .B} dst
Operation 0 −> dst
Emulation MOV{.W or .B} #0,dst
Description The destination operand is cleared.
Status Bits Status bits are not affected.
Example
CLR TONI ; 0 −> TONI
CLR R5
CLR.B TONI ; 0 −> TONI |
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Term
| Disable General Interrupts |
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Definition
DINT Disable (general) interrupts
Syntax DINT
Operation 0 → GIE or (0FFF7h .AND. SR → SR
Emulation BIC #8,SR
Description All interrupts are disabled. The constant 08h is inverted and logically ANDed with the status register (SR). The result is placed into the SR.
Status Bits Status bits are not affected.
Note: If any code sequence needs to be protected from interruption, the DINT should be executed at least one instruction before the beginning of the uninterruptible sequence, or should be followed by a NOP instruction |
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Term
| Enable General Interrupts |
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Definition
EINT Enable (general) interrupts
Syntax EINT
Operation 1 → GIE or (0008h .OR. SR −> SR)
Emulation BIS #8,SR
Description All interrupts are enabled. The constant #08h and the status register SR are logically ORed. The result is placed into the SR.
Status Bits Status bits are not affected.
Note: The instruction following the enable interrupt instruction (EINT) is always executed, even if an interrupt service request is pending when the interrupts are enable. |
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Term
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Definition
NOP No operation
Syntax NOP
Operation None
Emulation MOV #0, R3
Description No operation is performed. The instruction may be used for the elimination of instructions during the software check or for defined waiting times.
Status Bits Status bits are not affected.
Examples MOV #0,R3 ; 1 cycle, 1 word
JMP $+2 ; 2 cycles, 1 word
MOV #100,R3 ; 2 cycles, 2 words |
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Term
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Definition
POP Pop word or byte from stack to destination
Syntax POP{.W or .B} dst
Operation @SP −> temp
SP + 2 −> SP
temp −> dst
Emulation MOV{.W or .B} @SP+,dst
Description The stack location pointed to by the stack pointer (TOS) is moved to the destination. The stack pointer is incremented by two afterwards.
Status Bits Status bits are not affected.
Note: The system stack pointer (SP) is always incremented by two, independent of the byte suffix. |
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Term
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Definition
RET Return from subroutine
Syntax RET
Operation @SP→ PC
SP + 2 → SP
Emulation MOV @SP+,PC
Description The return address pushed onto the stack by a CALL instruction is moved to the program counter. The program continues at the code address following the subroutine call.
Status Bits Status bits are not affected. |
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Term
| Rotate Left Arithmetically |
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Definition
RLA Rotate word or byte left arithmetically
Syntax RLA{.W or .B} dst
Operation C MSB MSB−1 .... LSB+1 LSB 0
Emulation ADD{.W or .B} dst,dst
Description The destination operand is shifted left one position. The MSB is shifted into the carry bit (C) and the LSB is filled with 0. The RLA instruction acts as a signed multiplication by 2. An overflow occurs if the result has changed sign.
Status Bits N: Set if result is negative, else reset
Z: Set if result is zero, else reset
C: Loaded from the MSB
V: Set if an overflow, else reset |
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Term
| Rotate Left Through Carry |
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Definition
RLC Rotate word or byte left through carry
Syntax RLC{.W or .B} dst
Operation C MSB MSB−1 .... LSB+1 LSB C
Emulation ADDC{.W or .B} dst,dst
Description The destination operand is shifted left one position. The carry bit (C) is shifted into the LSB and the MSB is shifted into the carry bit (C).
Status Bits N: Set if result is negative, else reset
Z: Set if result is zero, else reset
C: Loaded from the MSB
V: Set if an arithmetic overflow, else reset |
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| system clock generator 1-turns off the SMCLK |
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| system clock generator 0-turns off the DCO dc generator |
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| Oscillator off-turns off the LFXT1 |
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| zero bit, when the result of an operand is zero |
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| when the result of an operation has a carry |
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Term
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Definition
Unified 64KB continuous memory map
Same instructions for data and peripherals
Program and data in Flash or RAM with no restrictions
Designed for modern programming techniques such as pointers and fast look-up tables |
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Term
| Anatomy of an Instruction |
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Definition
Opcode
What the instruction does – verb
May or may not require operands – objects
Source Operand
1st data object manipulated by the instruction
Destination Operand
2nd data object manipulated by the instruction
Also where results of operation are stored.
Addressing Modes |
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Term
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Definition
Unified 64KB continuous memory map
Same instructions for data and peripherals
Program and data in Flash or RAM with no restrictions
Designed for modern programming techniques such as pointers and fast look-up tables |
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Definition
15 14 13 12 11 10 9 8 7 - 6 - 5 4 - 3 2 1 0
op code ad as dest/source |
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15 14 13 - 12 11 10 - 9 8 7 6 5 4 3 2 1 0
op code condition 10 bit 2's compliment offset |
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Term
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The MSP430 has four basic modes for the source address:
Rs - Register
x(Rs) - Indexed Register
@Rs - Register Indirect
@Rs+ - Indirect Auto-increment
In combination with registers R0-R3, three additional source addressing modes are available:
label - PC Relative, x(PC)
&label – Absolute, x(SR)
#n – Immediate, @PC+ |
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Term
| Destination addressing modes |
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Definition
There are two basic modes for the destination address:
Rd - Register
x(Rd) - Indexed Register
In combination with registers R0/R2, two additional destination addressing modes are available:
label - PC Relative, x(PC)
&label – Absolute, x(SR) |
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Term
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Definition
The most straightforward addressing mode and is available for both source and destination
Example:
mov.w r5,r6 ; move word from r5 to r6
The registers are specified in the instruction; no further data is needed
Also the fastest mode and does not require an addition cycle
Byte instructions use only the lower byte, but clear the upper byte when writing |
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Definition
The address is formed by adding a constant (index) to the contents of a CPU register
Example:
mov.b 3(r5),r6 ; move byte from
; M(310+r5) to r6
Indexed addressing can be used for source and/or destination, value in r5 is unchanged.
The index is located in the memory word following the instruction and requires an additional memory cycle
There is no restriction on the address for a byte, but words must lie on even addresses |
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| Symbolic Mode (PC Relative) |
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Definition
The address if formed by adding a constant (index) to the program counter (PC)
Example: (mov.w x(PC), r6 where x=Cnt-PC)
mov.w Cnt,r6 ; move word
; M(Cnt+PC) to r6
The PC relative index is calculated by the assembler
Produces position-independent code, but rarely used in the MSP430 because absolute addressing can reach all memory addresses
Note: this is NOT an appropriate mode of addressing when referencing fixed locations in memory such as the special function registers (SFR’s) |
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Definition
The address is formed directly from a constant (index) and specified by preceding a label with an ampersand (&)
Example: (mov.w x(SR), r6 where 0 is used for SR)
mov.w &Cnt,r6 ; move word
; M(Cnt) to r6
Same as indexed mode with the base register value of 0 (by using the status register SR as the base register)
The absolute address is stored in the memory word following the instruction and requires an additional cycle
Note: this is the preferred mode of addressing when referencing fixed locations in memory such as the special function registers (SFR’s) |
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Term
| Indirect Register Mode (@Rn) |
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Definition
The address of the operand is formed from the contents of the specified register
Example:
mov.w @r5,r6 ; move word
; M(r5) to r6
Only available for source operands
Same as indexed mode with index equal to 0, but does not require an additional instruction word
The value of the indirect register is unchanged |
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Term
| Indirect Register Mode (@Rn) |
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Definition
The address of the operand is formed from the contents of the specified register
Example:
mov.w @r5,r6 ; move word
; M(r5) to r6
Only available for source operands
Same as indexed mode with index equal to 0, but does not require an additional instruction word
The value of the indirect register is unchanged |
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Term
| Indirect Autoincrement Mode (@Rn+) |
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Definition
The address of the operand is formed from the contents of the specified register and afterwards, the register is automatically increment by 1 if a byte is fetched or by 2 if a word is fetched
Example:
mov.w @r5+,r6 ; move word
; M(r5) to r6
; increment r5 by 2
Only available for source operands.
Usually called post-increment addressing.
Note: All operations on the first address are fully completed before the second address is evaluated |
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Term
| Indirect Autoincrement Mode (@Rn+) |
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Definition
The address of the operand is formed from the contents of the specified register and afterwards, the register is automatically increment by 1 if a byte is fetched or by 2 if a word is fetched
Example:
mov.w @r5+,r6 ; move word
; M(r5) to r6
; increment r5 by 2
Only available for source operands.
Usually called post-increment addressing.
Note: All operations on the first address are fully completed before the second address is evaluated |
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Term
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Definition
The operand is an immediate value
Example (mov.w @PC+, r6)
mov.w #100,r6 ; 100 -> r6
The immediate value is located in the memory word following the instruction
Only available for source operands
The immediate mode of addressing is a special case of auto-increment addressing that uses the program counter (PC) as the source register.
The PC is automatically incremented after the instruction is fetched; hence points to the following word |
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Term
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Definition
The operand is an immediate value
Example (mov.w @PC+, r6)
mov.w #100,r6 ; 100 -> r6
The immediate value is located in the memory word following the instruction
Only available for source operands
The immediate mode of addressing is a special case of auto-increment addressing that uses the program counter (PC) as the source register.
The PC is automatically incremented after the instruction is fetched; hence points to the following word |
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Term
| The Von Neumann Bottleneck |
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Definition
You may hear of the term “Von Neumann Bottleneck”
All instructions / data has to be fetched from memory
the path to memory is a bottleneck
In spite of this, the Von Neumann model is today’s computing model |
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Definition
Address Space = amount of data that can be stored (also called the memory size)
Addressability = number of bits stored in each memory location
1 byte = 8 bits
1 Kilobyte (KB) = 210 bytes = 1024 bytes
1 Megabyte (MB) = 220 bytes
1 Gigabyte (GB) = 230 bytes
1 Terabyte (TB) = 240 bytes
1 Petabyte (PB) = 250 bytes
1 Exabyte (EB) = 260 bytes |
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Term
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Definition
Memory Address Bus
Memory Address Register (MAR) stores the memory address for the address bus (address space)
used to address peripherals as well as memory
Memory Data Bus
Memory Select (MSEL) connects memory to the data bus (addressability)
Memory Write Enable (MWE) is the control signal that is asserted when writing to memory
bi-directional bus |
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Term
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Definition
ALU (Arithmetic and Logic Unit) performs the arithmetic and logical operations
Arithmetic operations: add, subtract, compare
Logical operations: and, xor, bit
Sets condition codes
The word length of a computer is the number of bits processed by the ALU. |
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Term
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Definition
The control unit directs the execution of the program
The program counter or PC points to the next instruction to be executed
The instruction register or IR contains the currently executing instruction
The status register or SR contains information about the last instruction executed as well as system parameters
The control unit prevents bus conflicts and timing/propagation problems
The control unit is a Finite State Machine driven by a clock |
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Term
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Definition
Interrupt vectors - Upper 16 words of Flash
Flash / ROM - Used for both code and data
RAM - Volatile storage
Peripherals
0100h – 01FFh 16-bit peripherals
0010h – 00FFh 8-bit peripherals
Special Function Registers - Lower 16 bytes |
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