Term
| how to define performance? |
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Definition
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Term
| how can you improve performance? |
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Definition
1. increase work
2. decrease time |
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Term
| write an equation for "Big is n% greater than Small" |
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Definition
1. (performance big - performance slow)/performance slow
2. (time slow - time fast)/time fast |
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Term
| write an equation for Tavg |
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Definition
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Term
| In order to optimize, what are two things that needs to be taken account? |
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Definition
| run time and frequency of occurence |
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Term
| what's a general rule to improve performance? |
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Definition
| make the common case faster |
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Term
| give an equation for time |
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Definition
| cycle * clockPeriod = numInstr*CPI*clockPeriod |
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Term
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Definition
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Term
| what does SPECint measure? |
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Definition
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Term
| if performance increase by 3 time every 12 months, give an equation of performance at t month |
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Definition
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Term
| What is functional validation? |
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Definition
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Term
| What is functional verification? |
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Definition
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Term
| What is formal verification? |
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Definition
| functional verification for every possible inputs |
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Term
| What is performance validation? |
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Definition
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Term
| What is power validation? |
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Definition
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Term
| What is equivalence verification? |
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Definition
| design generated by synthesis tool has same behavior as RTL code? |
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Term
| what is timing verification? |
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Definition
| all paths meet time constraints? |
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Term
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Definition
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Term
| if we have n bits of inputs and k bits of flops, how many different cases when doing functional verification? |
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Definition
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Term
| What are two characteristics for test bench? |
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Definition
1. no inputs or outputs
2. test bench only used for primary input and output |
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Term
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Definition
| when check behavior of internal signals |
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Term
| What is DUT in test bench? |
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Definition
| circuit that you are checking |
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Term
| What is stimulus in test bench? |
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Definition
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Term
| What is specification in test bench? |
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Definition
| describes desired behavior of implementation |
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Term
| What is check in test bench? |
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Definition
| checks whether implementation obeys specification |
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Term
| Draw a diagram for a normal test bench |
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Definition
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Term
| Draw a diagram for reference model test bench |
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Definition
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Term
| When are reference model test bench used? |
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Definition
check if output has a specific value
e.g DSP filters, instruction decoder, datapath |
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Term
| Draw a diagram for relational test bench |
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Definition
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Term
| When are relational test bench used? |
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Definition
based on relationship of input and output
e.g carry-save adders, control circuits |
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Term
| Datapath circuits are suitable for what kind of test bench? What about control circuits? |
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Definition
Datapath = reference
Control = relational |
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Term
| Why control circuits are often more challenging to verify? |
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Definition
1. has internal signals which test bench can't check
2. bugs can exists in any clock cycle and test bench doesn't know which cycle the bug is at |
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Term
| How to resolve the issue of bug at certain clock cycle? |
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Definition
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Term
| What is the goal of coverage monitor |
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Definition
| certain event is exercised in a simulation run or not |
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Term
| What's the pro and con of using function in VHDL? |
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Definition
Pro: flexible
con: verbose |
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Term
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Definition
| the difference in arrival times for the same clock edge at different flop |
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Term
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Definition
difference in arrival times for the same clock edge at different levels of interconnect along the clock tree
clock latency doesn't affect the limit on minimum clock eriod |
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Term
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Definition
| difference between actual clock period and ideal clock period |
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Term
| what are 2 causes of clock jitter? |
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Definition
1) tmp and voltage variations over time
2) different manufacturer |
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Term
| What is the difference between behavior of flop and latch? |
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Definition
| flop is edge sensitive and latch is level sensitive |
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Term
| When does setup time occur? |
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Definition
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Term
| When does hold time occur? |
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Definition
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Term
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Definition
| delay from the clock edge to when the output is guaranteed to be stable |
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Term
| What is propagation delay? |
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Definition
| time it takes a signal to travel from the source flop to destination flop |
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Term
| What's the equation for propagation delay? |
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Definition
| load delay + interconnect delay |
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Term
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Definition
| combinational gates between the flops |
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Term
| what is interconnect delay? |
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Definition
| wires between gates and flops |
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Term
| that's the equation for clock period? |
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Definition
| clockP > skew + jitter + Tco + propagation + setup |
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Term
| is the equation for clock period independent of hold time? |
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Definition
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Term
| what's the equation for hold constraint? |
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Definition
| skew + jitter + Tho < Tco + prop |
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Term
| when does setup violation occur? |
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Definition
| clock-to-Q + prop delay is too big |
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Term
| when does hold violation occur? |
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Definition
| before hold time ends, data changes |
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Term
| what 3 things needs to be identified to calculate setup and hold time? |
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Definition
1. how data is stored when not connected to input
2. the gates that the clock uses to cause the stored data to drive the output
3. the gates that the clock uses to cause the input to drive the output |
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Term
| when does setup start? when does it end? |
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Definition
start: when data start to propagate
end: when data finish to propagate |
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Term
| when can data, w/a, occur? |
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Definition
at t=0, input has w and output has a
then at t=1, output will have w/a |
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Term
| when does hold start? when does it end? |
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Definition
start: when data start to enter key gate
end: when the other data start to enter key gate |
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Term
| what's common about start and end of hold time and setup time? |
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Definition
start: there is a key gate which one of the signal starts to enter
end:both signals enter key gate |
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Term
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Definition
| the slowest path on the chip between flops or flops and pins. |
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Term
| what's the effect of critical path |
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Definition
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Term
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Definition
change in input doesn't affect change in output.
makes people believe they are critical path, but in reality, it's not a critical path |
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Term
| what's an algorithm to determine the critical path? |
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Definition
1. find longest path ignoring false path
2. test if the path is false path or not
3. choose next longest path if it's false path
4. do a correct, complete, and complex algorithm to find the critical path in a circuit |
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Term
| need to put rest of the questions after understanding rest of chapter 5 |
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Definition
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Term
| what's the equation for energy? |
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Definition
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Term
| what's the equation for power given v and i? |
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Definition
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Term
| when we talk about power, what is it usually about? |
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Definition
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Term
| when we talk about energy, what is it usually about? |
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Definition
| battery life or energy costs |
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Term
| what's equation for "power efficiency"? |
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Definition
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Term
| how to calculate energy given v and AH? |
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Definition
| convert hour to second, keep in mind ampere is in I/s |
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Term
| clock speed is proportional to what? |
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Definition
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Term
| what is the equation for power for hardware? |
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Definition
| switch power + short power + leakage power |
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Term
| how much energy is needed to charge a capacitor? |
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Definition
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Term
| what's the charged energy on a capacitor? |
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Definition
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Term
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Definition
| frequency at which inverter goes through complete charge-discharge cycle |
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Term
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Definition
| average number of times the signal switches from 0->1 or 1->0 per clock cycle |
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Term
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Definition
| 0.5*activity factor*clock speed |
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Term
| what's average switching power in terms of f'? |
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Definition
| f' * energy needed to charge capacitor to v |
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Term
| what's equation for short circuit power? |
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Definition
| activity factor * clock speed * timeshort * power needed to store to capacitor |
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Term
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Definition
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Term
| what's leakage current proportional to? |
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Definition
| exp[(-q*voltThresh)/(k*T)] |
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Term
| what two categories you can divide power reduction to? |
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Definition
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Term
| what are parameters to reduce power in analog level? |
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Definition
| capacitance, resistance, voltage |
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Term
| what are parameters to reduce power in digital level? |
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Definition
| capacitance, activity factor, clock frequency |
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Term
| what are 5 techniques for reducing power in analog level? |
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Definition
| dual-VDD, dual-Vt, exotic circuits, adiabatic circuits, clock trees |
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Term
| what are 5 techniques for reducing power in digital level? |
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Definition
| multiple clocks, clock gating, data encoding, glitch reduction, asynchronous circuits |
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Term
| what is dual-VDD power reduction technique? |
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Definition
| two different supply voltages. High voltage for performance-critical portions for design, low voltage for remainder of the circuit |
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Term
| what is dual-Vt power reduction technique? |
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Definition
| two different threshold voltages. low threshold voltage for high performance, high threshold voltage for low performance |
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Term
| what's exotic circuits in power reduction technique? |
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Definition
| special circuits that run high frequency while minimizing power |
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Term
| what's adiabatic circuits in power reduction technique? |
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Definition
| special circuits that consumes power on 0->1 transitions but not 1->0 transitions. Bad thing is this sacrifices performance |
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Term
| what's clock trees in power reduction technique? |
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Definition
| up to 30% of total power can be consumed in clock generation and clock tree |
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Term
| what's multiple clocks in power reduction technique? |
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Definition
| high speed clock in high performance circuit, low speed close for remainder of circuit |
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Term
| what's clock gating in power reduction technique? |
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Definition
| turn off portion of clock when not needed |
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Term
| what's data encoding in power reduction technique? |
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Definition
| gray coding vs one-hot vs fulling encoded |
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Term
| what's glitch reduction in power reduction technique? |
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Definition
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Term
| what's asynchronous circuits in power reduction technique? |
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Definition
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Term
| what's power proportional to for hardware? |
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Definition
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Term
| what will happen to hardware when we increase the supply voltage? |
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Definition
| decrease delay through a circuit |
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Term
| what's max clock speed proportional to in terms of Vsupply and Vthresh? |
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Definition
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Term
| what will happen to Ileak as Vthresh is decreased? |
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Definition
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Term
| what is power proportional to in terms of Ileak? |
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Definition
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Term
| what's effectiveness of clock gating? |
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Definition
| % of time there is invalid data, clock if off |
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Term
| what's %valid for clock gating? |
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Definition
| % of clock cycles with valid data in circuit the clock must be toggling |
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Term
| what's %clk for clock gating? |
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Definition
| percentage of clock cycles that clock toggles |
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Term
| what's equation for effectiveness of clock gating? |
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Definition
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Term
| what happens to effectiveness of clock gating if clock toggles only when there is valid data? |
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Definition
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Term
| what happens to effectiveness of clock gating if clock always toggles? |
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Definition
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Term
| in clock gating, what happens if %clk < %valid? |
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Definition
| turning off clock when shouldn't |
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Term
| what's the new activity factor given clock gating? |
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Definition
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