Term
What are the three addressing modes? |
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Definition
1. Literal 2. Direct 3. Indirect |
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Term
What are the three instruction modes? |
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Definition
1. memory-to-register (LDR)
2. Register-to-memory (STR)
3. Register-to-register ( |
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r0 to r11 are referred to as ______-________ registers |
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Definition
general-purpose registers |
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Definition
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Definition
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Term
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Definition
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What 4 flags does the CCR contain and what do they stand for? |
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Definition
Z-zero, N-negative, C-carry, V-overflow |
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Term
What hardware implements a Z flag? |
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Definition
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Term
What hardware implements a C flag? |
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Definition
Carry out from 31 bit full adder. Carry is only for addition |
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Term
What hardware implements an N flag? |
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Definition
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Term
What hardware implements an V flag? |
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Definition
The sign for both operands is the same but the outcome has a different sign. Overflow is only for addition and subtractiong |
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Term
What 3 things does the Instruction Set Architecture include? |
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Definition
1. Register set 2. Addressing modes 3. Instructions and formats |
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Definition
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Term
What does this instruction mean? LDR r2, [r3, #8] |
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Definition
Copy the contents of memory pointed at by register r3 plus 8 into register 2 -effective address- take the contents of register 3, add 8 to them, and this is the address to the data |
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Term
What does this instruction mean? MOV r2, [12, bx] |
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Definition
Copy the contents of memory pointed at by register bx plus 12 into register 2 |
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Term
What does this instruction mean? MOV r0, #12 |
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Definition
Copy the literal value 12 into register r0 |
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Term
What does this instruction mean? LDR r2, [r0, r1] |
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Definition
[r2]<- [[r0] + [r1]] Load r2 with the locations pointed at by r0 plus r1 |
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Term
What does this instruction mean? LDR r2, [r0, r1, LSL#2] |
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Definition
[r2]<-[[r0] + 4*[r1]] Load r2 with the location of r0 plus r1 scales by 4 |
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Term
What does this instruction mean? LDR r0, [r1,#8]! |
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Definition
Load r0 with the word pointed at by register r1+8, then update the pointer by adding 8 to r1
[r1]<-[r1]+8 r0 <-[[r1]] |
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Term
What does this instruction mean? LDR r0, [r1],#8 |
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Definition
Load register r0 with the word pointed at by r1, then do the post indexing by adding 8 to r1
[r0] <-[[r1]] [r1]<-[r1]+8 (update the pointer by adding the offset) |
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Term
The Condition Code Register (CCR) is also known as the |
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Definition
Current Processor Status Register |
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Term
What are assembler directives? |
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Definition
They tell the assembler how to assemble your code |
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Term
What is contained in the Program Counter register? |
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Definition
The next instruction to execute |
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Term
What is contained in the Memory Address Register? |
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Definition
It contains the address in memory that we either need to read from or write to |
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Term
What is in the instruction register? |
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Definition
It contains the current instruction being executed |
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Term
What is in the memory buffer register [MBR]? |
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Definition
It contains the data that is either being read from or written to memory |
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Term
What does the Arithmetic Logical Unit do? |
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Definition
It performs operations on 1 (unary), two (binary) or 3 (ternary) operands |
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Term
What are the different types of memory? |
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Definition
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Term
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Definition
They allow the transfer of memory from various locations within the CPU, memory, IO devices, etc. |
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Term
What does the control unit do? |
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Definition
Based on the instructions and addressing modes sends signals to all the registers, ALU, buses, memory, input/output devices to execute the instructions |
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Term
What are the three types of registers? |
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Definition
1. general purpose registers 2. special purpose registers 3. invisible registers |
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Term
Describe the general purpose registers |
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Definition
these are the registers that can be accessed and used by the programmer |
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Term
Describe the special purpose registers |
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Definition
These are the registers that can be affected by the programmer but not directly accessed, like the program counter, the CCR, and stack pointer |
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Term
Describe invisible registers |
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Definition
Invisible registers are needed by the CPU but cannot be directly accessed by the programmer. This includes the MAR, IR, and the MBR |
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Term
The address bus connects these pieces of the cpu |
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Definition
The Program Counter, Memory address registers and Operands part of IR |
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Term
The data bus connects these pieces of the cpu |
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Definition
The operand part of the IR, MBR, Registers, and ALU |
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Term
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Definition
takes your assembly code and converts it to machine code (or executable code) |
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Term
What are assembler directives? |
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Definition
tell the assembler how to assemble your code |
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Term
What are the 4 assembler directives we need to know for the test? |
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Definition
1. .text 2 .data 3. .global 4. .end |
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Term
Describe the .text assembler directive? |
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Definition
It is the start of the code and it is read only |
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Term
Describe the .data assembler directive? |
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Definition
This section should be defined after the .text and it is read/write section |
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Term
Describe the .global assembler directive |
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Definition
This is used for any external calls like printf, scanf, etc. |
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Term
Describe the .end assembler directive |
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Definition
This tells the assembler that this is the end of the code and followed by a blank line |
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Term
In the debugger, which command assembles the code? |
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Definition
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Term
In the debugger, which command links the code? |
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Definition
gcc (resolves external references) |
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Term
In the debugger, which command runs the code? |
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Definition
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Term
How/why do you use .asciz? |
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Definition
used in the .data section. It adds the null terminator onto the end of the string so you don't have to |
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Term
How does ARM do negation? |
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Definition
Turns all the 0s to 1s and 1s to 0s (1s complement) |
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Term
How do you handle a potential overflow in multiplication? |
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Definition
Need to detect when that does happen, use UMULL
UMULL regL, regU, regA, regB [regU, regL] <- [regA]* [regB]
If it fits into 32 bits, then it will be in regL CMP with regU, if it's 0, then you're good to go |
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Term
What are the 3 ways that you can pass values to a function in ARM? |
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Definition
1. Registers 2. The stack 3. Global variables |
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Term
What command unstacks and restores the CPSR? |
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Definition
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Term
With IRQ/FIQ interruptions, how do you change back from exception mode? |
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Definition
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Term
What hardware is used to implement a 32-bit adder? |
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Definition
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