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| A command that computer hardware understands and obeys |
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| A program that translates high level language statements into assembly language statements |
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| Location of programs and data when they are running |
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| Abstract interface between hardware and low level software, encompasses information needed to write a machine language program |
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| Model that renders low level details of computer systems invisible to facilitate design of systems. Omits unneeded information and helps deal with complexity. |
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| the part of the processor that performs arithmetic |
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| hardware that obeys architecture abstraction |
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| small, fast memory that acts as a buffer for slow, large memory |
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| program that managed computer resources |
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| the observation that over the |
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| number of tasks completed per unit of time |
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| What is the formula for performance? |
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| Performance(x) = 1 / Execution Time(x) |
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| State 4 formulas for CPU Time |
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Definition
CPU Clock Cycles x Clock Cycle Time CCC / CR Instruction Count x CPU x CCT Instruction Count x CPI / CR Sum(#ins for class i * CPI(i)) * cycle time |
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| What is the formula for CPU Clock Cycles? |
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| CPU Clock Cycles = # Instructions x Average Clock Cycles Per Instruction (CCI) |
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| Number of clock cycles each instruction takes to execute |
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| What are the formulas for calculating Number of CPU Clock Cycles? |
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CPI x #Ins Time x Clock Rate Summation (n, i=1) (CPIi x Ci) |
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| What are the formulas for CPI? |
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CCC / Instruction Count Total Cycles/#Ins Time * CR /#Ins Sum[(#ins for class i/total #ins)*CPI(i)] |
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| System performance and evaluation cooperation, Selective benchmarks taken from various applications |
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| What is the formula for throughput? |
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| One instruction per clock cycle |
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| Define: Superscalar processors |
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| Instruction dependencies determined at runtime dynamically by hardware, dynamic hw scheduling |
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| Very Large Instruction Word Processors |
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| What are the tree "walls" that hinder performance improvement? |
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| Name the 4 design principals discussed in class |
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| Simplicity Favours Regularity, Smaller is Faster, Make the Common Case Fast, Good Designs Demand Good Compromises |
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| Define: Temporal Locality |
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| The tendency to reuse recently accessed items |
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| The tendency to reference items close to other recently accessed items |
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| A circuit with only 1 output asserted for each input combination |
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| A circuit decoder that generates n signals, each indicated a different input value |
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| A set of locations that can be read, number of addressable entries determines number of addressable lines (2^n height) |
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| A collection of data lines treated as a single logical signal |
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| A free running signal with a fixed cycle time (period) with two positions, high and low |
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| What is the stored program concept? |
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| Storage of instructions in computer |
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Term
| What does an R type instruction look like? |
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Definition
| Op(6), Rs(5), Rt(5), Rd(5), Shamt(5), Function(6). Op = 000000 |
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| What does an I type instruction look like? |
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Definition
| Op(6), Rs(5), Rt(5), Addr(16). Op != 000000 |
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| Name the FU's discussed in class? |
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Definition
| RegDST, PCSrc, MemRead, MemToReg, ALUOp, MemWrite, ALUSrc, RegWrite |
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Term
| What is the function of RegDST? |
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Definition
| A MUX that determines which register we use as a destination (I versus R instructions) |
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Term
| What is the function of MemToReg? |
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Definition
| MUX that determines the data for the destination register (ALU result or data memory) |
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Term
| What is the function of ALUSrc? |
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Definition
| MUX that determines 2nd input to ALU (register or offset address - IMM) |
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Term
| What is the function of the Branch Control Line? |
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Definition
| Determines if we use PC+4 or PC+4+Offset (branch conditional) |
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| What are the ALU controls? |
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Definition
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| Describe how an R type instruction is executed? |
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Definition
| Ins fetched, PC incremented. 2 Reg's read. ALU operates on 2 reg's data. Result of ALU written into registers |
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Term
| Describe how an LW type instruction is executed? |
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Definition
| Ins fetched, PC+=4, Reg's read, ALU adds reg data with offset, ALU result used as addr to read data from memory, data from memory written into reg file |
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Term
| Describe how a BEQ type instruction is executed? |
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Definition
| Ins fetched, Pc+=4, 2 reg's read from reg file, ALU subtract on data values read from reg file, PC+4 added to SE. lower 16 bits shifted 2 L, result of is branch target address, zero result from ALU used to decide which adder result to store into PC |
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| Give an example of a critical path for R-Format instructions |
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Definition
| Instruction Memory, Reg File, ALU, Reg File |
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| Give an example of a critical path for LW instructions |
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Definition
| Instruction Memory, Reg File, ALU, Data Memory, Reg File |
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| Give an example of a critical path for SW instructions |
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Definition
| Instruction Memory, Reg File, ALU, Data Memory |
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| Give an example of a critical path for Branch instructions |
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Definition
| Instruction Memory, Reg, ALU, Adder |
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| Give an example of a critical path for Jump instructions |
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Definition
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| What is the formula for comparing the performance of two systems? |
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Definition
| P(X)/P(Y) = n = E(Y)/E(X) |
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| What is the formula for calculating clock rate? |
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Definition
Cycles/second (I * CPI) / CPU Time |
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| What is the formula for calculating Seconds/Program? |
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Definition
| Cycles/Program * Seconds/Cycle |
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| What is the formula for MIPS? |
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Definition
| # Ins / (Execution Time x 10^6) |
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