Term
| Historically, what has been the relationship between latency and bandwidth? Explain |
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Definition
| Bandwidth has improved faster than latency, due to both architectual and commercial reasons |
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Term
| Give one reason CPU implementation is becoming as important (if not more) as instruction set design in influencing CPU performance. |
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Definition
| Instruction set architectures (ISA) have converged, while implementation options (e.g., pipelining, superscalar, multicore) for the same ISA have a major impact on CPU performace |
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Term
| Give one reason computer architects use benchmarks instead of real programs to measure computer performance. |
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Definition
| Benchmarks provide reproducible results that are easy to compare across computing platforms, and are easier to use than real programs. |
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Term
| Why do computer architects prefer using geometric mean instead of arithmetic or harmonic mean when presenting benchmark results? |
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Definition
| Results are consistent regardless of choice of reference platform |
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Term
| What is a structural hazard? |
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Definition
| Hardware limitation preventing pipeline instruction from executing (e.g., single-ported memory) |
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Term
| Why are RAW hazards fundamentally different than WAR and WAW hazards? |
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Definition
| RAW hazards represent actual flow of values, whereas WAR and WAW hazards are name dependences caused by reuse of storage (and can be eliminated using additional storage) |
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Term
| Explain why exceptions are problematic for pipelined processors. |
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Definition
| Because when an exception occurs, both previous & succeeding instructions may be still executing in the pipeline, and need to be handled before the exception can be processed. |
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Term
| Describe the difference between synchronous and asynchronous exceptions. |
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Definition
| Synchronous exceptions occur when a particular instruction is executed. Asynchronous exceptions may occur any time. |
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Term
| Explain why pipelined processors face additional problems when certain instructions (e.g., mult) require more time (i.e., clock cycles) to complete. |
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Definition
| Instructions may complete out of order, requiring additional checks to avoid data hazards. |
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Term
Explain why filling the branch delay slot with an instruction from before the branch is preferred to the alternatives.
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Definition
| If permitted by language semantics, putting an instruction from before the branch will not introduce extra execution costs regardless of whether branch is actually taken |
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Term
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Definition
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Term
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Definition
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Term
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Definition
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Term
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Definition
| At the execute stage of a cycle, it passes information to the next cycle |
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Term
When do we find out that the PC needs to
be modified? |
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Definition
Answer: In pipeline stage ID of a branch
instruction
So, if a branch is not-taken (i.e., if the PC is notmodified), need a one-cycle delay |
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Term
Question: When is a taken branch’s address known?
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Definition
ALU used to compute, so EX stage
Need two (or three) cycle delay |
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Term
| What are the 4 branch hazard alternatives? |
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Definition
1. Stall untill branch direction is clear
2. Predict branch not taken (47%)
3. Predict branch taken (53%)
4. Delayed branch |
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Term
| Question: What makes pipelining hard to implement? |
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Definition
| Exceptions, faults, interrupts |
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Term
15
Give Some Examples Of Exceptions
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Definition
Request for I/O
•
Arithmetic troubles: overflow or underflow
•
Cache miss: data not in (on-chip) cache memory
•
Page fault: data not in (physical) memory
•
Illegal address, giving a memory protection
violation
•
Hardware failure |
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Term
| When Do MIPS Exceptions Occur? |
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Definition
IF: -Page fault on instruction fetch
-misaligned memory access
-memory protection violation
ID: -undefined or illegal opcode
EX:-arithmetic exception
MEM:-page fautl on data fetch/store
-misaligned memory access
-memory protection violation
WB:None! |
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Term
| How many cycles do MIPS instructions take? |
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Definition
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Term
| What are the 4 major causes of pipeline stalls? |
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Definition
load stalls – from using load result 1 or 2
cycles after load
branch stalls – 2 cycles on every taken branch,
or empty branch delay slot
FP result stalls – RAW hazards for an FP
operand
FP structural stalls – from conflicts for
functional units in FP pipeline |
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Term
CS252 S05
CMSC 411 - 13 (some from Patterson, Sussman, others)
21
How to reduce the miss rate? |
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Definition
•Use larger blocks
• Use more associativity, to reduce conflict misses
• Victim cache
• Pseudo-associative caches (won’t talk about this)
• Prefetch (hardware controlled)
• Prefetch (compiler controlled)
• Compiler optimizations |
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Term
| Why are cache misses sometimes inevitable? |
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Definition
Compulsory miss » The first time a block is used, need to bring it into cache
Capacity miss » If need to use more blocks at once than can fit in to cache, some will bounce in and out
Conflict miss » In direct mapped or set associative caches, there are certain combinations of addresses that cannot be in cache at the same time |
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Term
| Explain how caches improve processor performance. |
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Definition
Because access to data in cache is faster than access to data in memory, and
temporal & spatial locality allows data in cache to
be reused once it is
brought in from memory. |
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Term
| Explain why pipelining improves processor performance |
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Definition
Performance is improved because pipelining allows instruction execution to
be overlapped with other instructions, allowing multiple instructions to be
executed at the same time |
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