Term
| What are the components of a computer at the Device Physical Level? |
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Definition
| Transistors, Atoms. What is used to make the gates |
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Term
| What is included at the CPU's Gate Level? |
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Definition
| Flip-flops, AND, OR, etc. gates. |
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Term
| What components are involved in the Microarchitecture - Microprogramming? |
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Definition
| Physical organization - registers, ALU, Bus, control unit. Determined at processor design time. |
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Term
| What's included on the Low-Level Language level? |
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Definition
| Architecture dependent and will only execute on one particular class of computer. ARM, Intel i7, etc. |
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Term
| What is the High-Level Language Level of processor control? |
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Definition
| Computer appears to be machine independent. All computers executing the same language are identical. Even if the program as to be compiled specifically for that target machine. |
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Term
| What is the application level of processor control? |
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Definition
| The computer appears to be a device that performs a function. GPS, Car stereo, Gaming system, smart phone, etc. |
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Term
| What is the fetch process? |
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Definition
[MAR] <-- [PC]
Get ready to fetch the next instruction from memory
[PC] <-- [PC] + 4
Point to the next instruction.
[MBR] <-- [[MAR]]
Read the instruction from memory and store results
[IR] <-- [MBR]
Transfer the instruction to the instruction register and start decode process. |
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Term
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Definition
| Multiple instructions are executing at the same time on the same CPU or core |
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Term
| What are the stages of the 5-stage pipeline? |
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Definition
1. IF - Instruction Fetch
2. ID - Instruction Decode - Depends on the complexity of the instruction
3. OF - Operand Fetch - Gets the data (if needed) that the instruction needs to execute upon.
4. Exec - Execute - Performs the operation specified by the instruction.
5. OS - Operand Store - Save the data to the specified location. |
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Term
| True or False. All instructions require all stages of the 5-stage pipeline? |
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Definition
| False. Not all instructions require all 5-stages. For example a CMP does not have the Operand Store stage. |
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Term
| How does parallel processing affect the hardware? |
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Definition
| Will have to have redundant hardware if it can be used by the different stages at the same time. For example the PC increment during the fetch cannot use the ALU that is used for the Execute stage. |
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Term
| How does parallel processing affect the software? |
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Definition
| There are cases where an operand read can happen prior to or at the same time as the operand write. Can get old data. The assembler has to know about this and reorganize the code to make sure this does not happen. |
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Term
| What are the 4 stages of the 4-stage pipeline? |
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Definition
1. Fetch
2. Operand read
3. Execute
4. Write Operand |
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Term
| In the pipeline speed formula, what do n and i stand for? |
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Definition
n = number of pipeline stages
i = number of operations performed in the pipeline
(n * i = how long it takes to perform i instructions without having a pipeline) |
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Term
| What is the overall concept to know about speed up? |
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Definition
| The more instructions that I have, the closer the speed up is to n |
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Term
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Definition
| problems that reduce the pipeline's throughput |
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Term
| What are structural hazards? |
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Definition
When you don’t have sufficient hardware to support the pipeline (only 1 ALU)
Done at design time of the CPU- nothing you can do about these |
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Term
| What are data/pipeline hazards? |
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Definition
It's when the pipeline has to wait until another step is complete
Data dependencies are bad for pipelines |
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Term
| What are the three types of data/pipeline hazards? |
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Definition
1.Read after write- this is a true data hazard
2. Write after write
3. Write after read
* 2 and 3 are only data hazards if the code is reordered/superscalar architecture |
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Term
| What is a control/branch hazard? |
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Definition
| It's when a branch instruction is executed and the pipeline is filled with incorrect instructions. This makes a bubble in the pipeline that has to be flushed out |
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Term
| How can you mitigate branch hazards? |
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Definition
1. Speculative execution- You can play the odds and assume the branch isn't taken
2. Freeze the Pipeline, where you stop loading more instructions once a branch is detected (freeze the pipeline) until you know if the branch is taken or not. Then adds the correct instructions.
3. Delayed branching where the compiler reorders the instructions so you don't have to freeze the pipeline (works 60% of the time) |
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Term
| What does it mean to squash/flush a pipeline? |
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Definition
| It means that the program took a branch and the pipeline is filled with incorrect instructions which have to be removed before proceeding. |
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Term
| What is start-up latency? |
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Definition
| It's the time it takes the pipeline to backfill after a branch is executed |
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Term
| What is a branch penalty? |
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Definition
| The cost (in terms of time) of executing an operation that causes a non-sequential flow of control. |
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Term
| What are the high-language constructs that cause branches? |
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Definition
1. Conditional statements (if, then, else, switch)
2. Loops (for, reap until, while, do while)
3. Conditional subroutine/function calls and the conditional return from them |
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Term
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Definition
| They don't contain anything in the pipeline- usually due to conditional branching |
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Term
| How does knowing about the effects of branching effect our programming? |
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Definition
| The most efficient program does not contain conditional branching, so the majority of the routes through the code should be in a straight flow to maximize efficiency |
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Term
| True or False, in speculative execution, the processor always assumes the branch is not taken |
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Definition
| True (this is hardwired into the CPU) |
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Term
| What are the two types of speculative execution? |
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Definition
1. static- usually set by whomever designed the architecture (usually don't branch)
2. dynamic- the CPU makes its own decision based on the information it has (uses the history) |
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Term
| What is contained in the branch target buffer? |
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Definition
| 1. Address of the branch instruction 2. Predicted outcome of the branch (take or not take) 3. Past history 4. Branch target address. 5. Copy of the instruction where the branch is located. |
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Term
| True or False: The prediction in the branch target buffer can be more than a single bit. |
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Definition
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Term
| What is branch pattern history? |
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Definition
| It keeps track of interactions between multiple branches i.e. the previous branch influences the current branch |
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Term
| True or False: The write after read and the write after write data hazards do not typically present problems with a pipeline CPU unless other speed-up techniques like instruction reorder or parallel execution are employed. |
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Definition
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Term
| True or False: A pipeline structural hazard happens when there is a data reference in one of the pipeline stages and the data is not ready for use. |
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Definition
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Term
| True or False: There are no drawbacks associated with implementation of a pipeline architecture for CPUs. |
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Definition
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Term
| True or False: Delayed branching uses a technique called reordering code to limit the negative effect of conditional branching in pipelined CPUs. |
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Definition
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Term
| True or False: Unconditional branches have no negative effect on modern pipelined CPUs. |
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Definition
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Term
| True or False: Every conditional branch instruction requires the pipeline to be flushed. |
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Definition
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Term
| What is the branch target buffer? |
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Definition
| it is special-purpose memory that stores information about the branch instructions that are currently active in the program |
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