Term
| Instruction level parallelism |
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Definition
The measurement of ability to perform two instructions at once based on two (or more) instructions not being dependent on the results of the other(s).
If I have the lines:
C=A+B
D=E+F
G=C+D
...I can't run the third line at the same time as the other two, because I need their results first. The first two lines, however, aren't dependent on each other, so they can be executed at the same time, if the compiler, or the CPU during run time, is smart enough to recognize and take advantage of it. |
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Term
| Superscalar (feature of CPU) |
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Definition
| A superscalar processor executes more than one instruction during a clock cycle by simultaneously dispatching multiple instructions to redundant functional units on the processor. Each functional unit is not a separate CPU core but an execution resource within a single CPU such as an arithmetic logic unit, a bit shifter, or a multiplier. NOT the same as pipelining, though they both are examples of instruction level parallelism and superscalar CPUs usually implement pipelining. |
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Term
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Definition
| Pipelining occurs when you have something set up in such a way where the output of one element is the input of the next one (meaning, first it has X done to it then the result has Y done to it). Instruction pipelining happens in a processor; the circuitry is usually divided up into stages, including instruction decoding, arithmetic, and register fetching stages, wherein each stage processes one instruction at a time. Once an instruction is done with a step and moves onto the next one, another instruction can follow behind (as long as they aren't dependent on each other's result; see instruction level parallelism for a clearer explanation of this requirement). |
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Term
| ALU, FPU (just what they stand for) |
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Definition
ALU = Arithmetic logic unit.
FPU = Floating-point unit. |
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Term
| MMU, PMMU (just what they stand for) |
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Definition
MMU = Memory management unit
PMMU = Paged memory management unit |
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Term
| TLB (just what it stands for) |
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Definition
| Translation lookaside buffer |
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Term
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Definition
It's a circuit on a processor that does what it says on the label: it does arithmetic and logic operations. For example, the vast majority can do:
* Integer arithmetic operations (addition, subtraction, and sometimes multiplication and division, though this is more expensive)
* Bitwise logic operations (AND, NOT, OR, XOR)
* Bit-shifting operations (shifting or rotating a word by a specified number of bits to the left or right, with or without sign extension). Shifts can be interpreted as multiplications by 2 and divisions by 2.
The more complex processors' ALUs can do more types of calculations. It would do you well to examine the pros and cons of this (ability vs. cost) |
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Term
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Definition
| A circuit on a processor that does what you'd expect: carry out operations on floating point numbers. Typical operations are addition, subtraction, multiplication, division, and square root. Some systems (particularly older, microcode-based architectures) can also perform various transcendental functions such as exponential or trigonometric calculations, though in most modern processors these are done with software library routines. |
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Term
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Definition
In Starfox 64, it is performed by pressing the Z-button twice; this spins your ship and effectively blocks lasers that are shot at you.
Wait, that's barrel ROLL. A barrel SHIFTER can shift, in a single clock cycle, a data word by a specified number of bits. For instance, let's say you have a 4-bit barrel shifter, given 4-bits of some value; call them ABCD. A barrel shifter can turn that into BCDA or CDAB or DABC. Thus, it can turn 0100 into 0010 or 0001 or 1000, depending if it's told to shift by 1, 2 or 3 bits. |
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Term
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Definition
| A bus that used to be used to connect the CPU to the CPU cache when it was off the chip (usually L2, like on the Pentium II and earlier PowerPC CPUs). Nowadays, generally they have integrated the L2 cache into the CPU's own silicon substrate. This shrinks the real estate requirements of the processing unit, cuts packaging costs and allows designers to move to lower-priced pipeline burst static RAM. Rather than needing an external wire to connect CPU and memory, chip designers could now incorporate the backside bus in silicon. Which, by definition, means it's no longer a bus. |
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